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r10ds0218ej0100 rev.1.00 page 1 of 16 oct 07, 2013 data sheet HN58C256AI series 256k eeprom (32-kword 8-bit) description renesas electronics' HN58C256AI are electrically erasab le and programmable roms organized as 32768-word 8-bit. they have realized high speed low power consumption and high reliability by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features ? single 5 v supply: 5 v 10% ? access time: 85 ns/100 ns (max) ? power dissipation ? active: 20 mw/mhz, (typ) ? standby: 110 w (max) ? on-chip latches: address, data, ce , oe , we ? automatic byte write: 10 ms max ? automatic page write (64 bytes): 10 ms max ? data polling and toggle bit ? data protection circuit on power on/off ? conforms to jedec byte-wide standard ? reliable cmos with mnos cell technology ? 10 5 erase/write cycles (in page mode) ? 10 years data retention ? software data protection ? there are lead free products r10ds0218ej0100 rev.1.00 oct 07, 2013
HN58C256AI series r10ds0218ej0100 rev.1.00 page 2 of 16 oct 07, 2013 ordering information orderable part name access time package shipping container quantity hn85c256api85e 85ns 600mil 28-pin plastic dip prdp0028ab-a (dp-28v) tube max. 13 pcs/tube max. 325 pcs/inner box hn85c256api10e 100ns hn85c256afpi85e 85ns 400mil 28-pin plastic sop prsp0028dc-a (fp-28dv) tube max. 25 pcs/tube max. 1,000 pcs/inner box hn85c256afpi10e 100ns hn85c256afpi85ez 85ns tape and reel 1,000 pcs/reel hn85c256afpi10ez 100ns hn85c256ati85e 85ns 28-pin plastic tsop ptsa0028zb-a (tfp-28dbv) tray max. 60 pcs/tray max. 600 pcs/inner box hn85c256ati10e 100ns pin arrangement hn58c256api/afpi series hn58c256ati series (top view) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HN58C256AI series r10ds0218ej0100 rev.1.00 page 3 of 16 oct 07, 2013 pin description pin name function a0 to a14 address input i/o0 to i/o7 data input/output oe output enable ce chip enable we write enable v cc power supply v ss ground nc no connection block diagram v v oe ce a5 a0 a6 a14 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch to to to
HN58C256AI series r10ds0218ej0100 rev.1.00 page 4 of 16 oct 07, 2013 operation table operation c e o e w e i/o read v il v il v ih dout standby v ih * 1 high-z write v il v ih v il din deselect v il v ih v ih high-z write inhibit v ih ? v il ? d a t a polling v il v il v ih dout (i/o7) program reset high-z note: 1. don?t care absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?0.6 to +7.0 v input voltage relative to v ss vin ?0.5 * 1 to +7.0 * 3 v operating temperature range * 2 topr ?40 to +85 c storage temperature range tstg ?55 to +125 c notes: 1. vin min: ?3.0 v for pulse width 50 ns 2. including electrical characteristics and data retention 3. should not exceed v cc + 1 v. recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 0 0 0 v input voltage v il ?0.3 * 1 ? 0.6 v v ih 3.0 ? v cc + 0.3 * 2 v operating temperature topr ?40 ? +85 c notes: 1. v il min: ?1.0 v for pulse width 50 ns 2. v ih max: v cc + 1.0 v for pulse width 50 ns
HN58C256AI series r10ds0218ej0100 rev.1.00 page 5 of 16 oct 07, 2013 dc characteristics (ta = ?40 to +85c, v cc = 5.0 v 10%) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2 a v cc = 5.5 v, vin = 5.5 v output leakage current i lo ? ? 2 a v cc = 5.5 v, vout = 5.5/0.4 v standby v cc current i cc1 ? ? 20 a c e = v cc i cc2 ? ? 1 ma c e = v ih operating v cc current i cc3 ? ? 12 ma iout = 0 ma, duty = 100%, cycle = 1 s, v cc = 5.5 v ? ? 30 ma iout = 0 ma, duty = 100%, cycle = 85 ns, v cc = 5.5 v output low voltage v ol ? ? 0.4 v i ol = 2.1 ma output high voltage v oh v cc 0.8 ? ? v i oh = ?400 a capacitance (ta = +25c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance * 1 cin ? ? 6 pf vin = 0 v output capacitance * 1 cout ? ? 12 pf vout = 0 v note: 1. this parameter is periodically sampled and not 100% tested.
HN58C256AI series r10ds0218ej0100 rev.1.00 page 6 of 16 oct 07, 2013 ac characteristics (ta = ?40 to +85c, v cc = 5.0 v 10%) test conditions ? input pulse levels: 0.4 v to 3.0 v ? input rise and fall time: 5 ns ? input timing reference levels: 0.8, 2.0 v ? output load: 1ttl gate +100 pf ? output reference levels: 1.5 v, 1.5 v read cycle parameter symbol hn58c256api/afpi/ati unit test conditions -85 -10 min max min max address to output delay t acc ? 85 ? 100 ns ce = oe = v il , w e = v ih ce to output delay t ce ? 85 ? 100 ns oe = v il , we = v ih oe to output delay t oe 10 40 10 50 ns ce = v il , we = v ih address to output hold t oh 0 ? 0 ? ns ce = oe = v il , w e = v ih oe ( ce ) high to output float * 1 t df 0 40 0 40 ns ce = v il , we = v ih write cycle parameter symbol min * 2 typ max unit test conditions address setup time t as 0 ? ? ns address hold time t ah 50 ? ? ns ce to write setup time ( we controlled) t cs 0 ? ? ns ce hold time ( we controlled) t ch 0 ? ? ns we to write setup time ( ce controlled) t ws 0 ? ? ns we hold time ( ce controlled) t wh 0 ? ? ns oe to write setup time t oes 0 ? ? ns oe hold time t oeh 0 ? ? ns data setup time t ds 50 ? ? ns data hold time t dh 0 ? ? ns we pulse width ( we controlled) t wp 100 ? ? ns ce pulse width ( ce controlled) t cw 100 ? ? ns data latch time t dl 50 ? ? ns byte load cycle t blc 0.2 ? 30 s byte load window t bl 100 ? ? s write cycle time t wc ? ? 10 * 3 ms time to device busy t db 120 ? ? ns write start time t dw 0 * 4 ? ? ns notes: 1. t df and t dfr are defined as the time at which the outputs ac hieve the open circuit conditions and are no longer driven. 2. use this device in longer cycle than this value. 3. t wc must be longer than this value unless polling techniques are used. this device automatically completes the internal write operation within this value. 4. next read or write operat ion can be initiated after t dw if polling techniques are used. 5. a6 through a14 are page address and these addr esses are latched at the first falling edge of we . 6. a6 through a14 are page address and these addr esses are latched at the first falling edge of ce . 7. see ac read characteristics.
HN58C256AI series r10ds0218ej0100 rev.1.00 page 7 of 16 oct 07, 2013 timing waveforms read timing waveform a ddress ce oe we data out high data out valid t acc t ce t oe t oh t df
HN58C256AI series r10ds0218ej0100 rev.1.00 page 8 of 16 oct 07, 2013 byte write timing waveform (1) ( we controlled) a ddress ce we oe din t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh v cc byte write timing waveform (2) ( ce controlled) a ddress ce we oe din t wc t ah t ws t as t oeh t wh t oes t ds t dh v cc t cw t bl
HN58C256AI series r10ds0218ej0100 rev.1.00 page 9 of 16 oct 07, 2013 page write timing waveform (1) ( we controlled) a ddress a 0 to a14 we ce oe din t as t ah t bl t wc t oeh t dh t oes v cc t ch t cs t wp t dl t blc t ds *7 page write timing waveform (2) ( ce controlled) a ddress a 0 to a14 we ce oe din t as t ah t bl t wc t oeh t dh t oes v cc t wh t ws t cw t dl t blc t ds *8
HN58C256AI series r10ds0218ej0100 rev.1.00 page 10 of 16 oct 07, 2013 data polling timing waveform t ce t oeh t wc t dw t oes a ddress ce we oe i/o7 t oe din x an an dout x dout x *9 *9 an toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from "1" to "0" (toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is "1". 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 a ddress *3 *3 *4 din
HN58C256AI series r10ds0218ej0100 rev.1.00 page 11 of 16 oct 07, 2013 software data protection timing waveform (1) (in protection mode) v ce we a ddress data 5555 aa 2aaa 55 5555 a0 t blc t wc cc write address write data software data protection timing waveform (2) (in non-protection mode) v ce we a ddress data t wc cc normal active mode 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 20
HN58C256AI series r10ds0218ej0100 rev.1.00 page 12 of 16 oct 07, 2013 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 s from the preceding falling edge of we or ce . when ce or we is high for 100 s after data input, the eeprom enters write mode automatica lly and the input data are written into the eeprom. data polling data polling indicates the status that the eeprom is in a wr ite cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs fr om i/o7 to indicate that the eeprom is performing a write operation. we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles. data protection to prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less. 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. be careful not to allow noise of a width of more than 20 ns on the control pins. we ce oe v 0 v v 0 v 20 ns max ih ih
HN58C256AI series r10ds0218ej0100 rev.1.00 page 13 of 16 oct 07, 2013 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins genera ted by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom shoud be kept in unprogrammable state during vcc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * * 2.1 protection by ce , oe , we to realize the unprog rammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : don?t care v cc : pull-up to vcc level v ss : pull-down to vss level 3. software data protection to prevent unintentional programming, this device has the software data protection (sdp) mode. the sdp is enabled by inputting the following 3 bytes code and write data . sdp is not enabled if only the 3 bytes code is input. to program data in the sdp enable mode, 3 bytes code must be input before write data. data aa 55 a0 write data } normal data input address 5555 2aaa 5555 write address the sdp mode is disabled by inputting the following 6 bytes code. note that, if data is input in the sdp disable cycle, data can not be written. data aa 55 80 aa 55 20 a ddress 5555 2aaa 5555 5555 2aaa 5555 the software data protection is not enabled at the shipment. note: there are some differences betw een renesas electronics' and other comp any?s for enable/disable sequence of software data protection. if there are any questions, please contact with renesas electronics' sales offices.
HN58C256AI series r10ds0218ej0100 rev.1.00 page 14 of 16 oct 07, 2013 package dimensions hn58c256api series (prdp0028ab-a / previous code: dp-28v) 15.24 maxnom min dimension in millimeters symbol reference 35.6 13.4 5.70 a 1 z b 3 d e a b p c e l e 1 0.51 0.58 1.2 0.20 0.25 0.36 2.29 2.54 2.79 0 15 36.5 14.6 0.38 0.48 1.9 2.54 15 28 14 1 3 1 p 1 c e z l a a b b e d e p-dip28-13.4x35.6-2.54 4.6g mass[typ.] dp-28/dp-28v prdp0028ab-a renesas code jeita package code previous code
HN58C256AI series r10ds0218ej0100 rev.1.00 page 15 of 16 oct 07, 2013 hn58c256afpi series (prsp0028dc-a / previous code: fp-28dv) f *1 *2 p mx y 1 e index mark 14 28 15 a z h e d b 1 1 p terminal cross section c b b c 1 1 detail f a l l q a l e c 1 b 1 d e a 2 b p c x y h e z l 1 18.3 1.7 0.20 0 8 11.8 0.12 0.17 0.22 0.38 0.48 0.10 0.20 0.30 8.4 0.15 0.8 1.0 1.2 2.50 reference symbol dimension in millimeters min nom max 18.8 a 1 0.32 0.40 12.1 11.5 1.27 0.15 1.12 note) 1. dimension"*1" does not include mold flash. 2. dimension"*2"does not include trim offset. e p-sop28-8.4x18.3-1.27 0.7g mass[typ.] fp-28d prsp0028dc-a renesas code jeita package code previous code
HN58C256AI series r10ds0218ej0100 rev.1.00 page 16 of 16 oct 07, 2013 hn58c256ati series (ptsa0028zb-a / previous code: tfp-28dbv) 0.45 0.10 0.55 13.10 13.70 0.220.14 a 1 8.20 max nommin dimension in millimeters symbol reference 1.20 0.600.500.40 0.15 8.00 0.200.130.05 0.30 0.20 0.220.170.12 13.40 5 0 0.10 0.80 11.80 l 1 z h d y x c b p a 2 e d b 1 c 1 e l a note) 1. dimension"*1"and"*2(nom)" do not include mold flash. 2. dimension"*3"does not include trim offset. f *1 *3 d p 1 mx y 14 28 15 index mark *2 e z b a e h d 1 1 p terminal cross section c b b c 1 1 detail f l l a q p-tsop(1)28-8x11.8-0.55 0.23g mass[typ.] tfp-28db/tfp-28dbv ptsa0028zb-a renesas code jeita package code previous code
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history hn58c256 ai series data sheet rev. date description page summary rev.1.00 oct 07, 2013 ? initial issue
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